As an aid in multiprocessing, many hosts employ what is termed virtual machines; each virtual machine is also referred to as a guest. Each guest has its own operating system and functions as an independent machine. The architecture of such a host includes a level 0 architecture having a central processor, hardware and microcode on which all of the programming constituting the host operating system and the quest operating systems resides. Such hardware includes a cache, a calculator, program status words, a main memory and the like, as is well known in the art. A level 1 architectural level for the host includes a system control program and hardware including main storage that operates with the above-described central processing hardware and microcode. Level 1 includes the host control, including its operating system. Level 2 includes all of the virtual machines with their respective operating systems. Level 3 includes all of the users in each of the respective virtual machines. All input and output operations for either the host or the various guests are intercepted by the host operating system such that all peripheral controls require host operating system intervention for each and every one of the virtual machines. Putting this statement another way, all peripheral operations are on a host basis rather than on a virtual machine basis. It is desired to enable the virtual machines to directly access peripheral systems in such a manner that system integrity is maintained and interruption of the host operating system by quest input-output operations is minimized.
In the above-described virtual environment, a paging and swapping storage system typically stores the programs of computer instructions and other control data associable with the various host operating system and guests. Other input-output is also connected to the various virtual machines through mechanisms similar to that provided for handling paging and swapping operations for establishing and continuing operations in the virtual environment. Because of the key nature of paging and swapping, the present invention is described in its best mode as applied to this aspect of peripheral systems in a virtual environment.
Input-output operations are typically handled in so-called chains of command, also referred to as IO chaining. Each chain of commands usually relates to a single source, such as the host operating system or one of the guests. A host control of such peripheral or input-output chains includes the peripheral system generation of logical and physical addresses for data stored or manipulated by the peripheral system. As an example, a peripheral system which can be a tape storage system assigns logical and physical values to arrange the data signals received from a host into blocks of such signals. The host can retrieve such assigned values for later use in locating blocks of signals as well as for error recovery purposes. In buffered peripheral systems, such logical and physical values assigned during execution of chains of command can identify current status of various data buffers in the peripheral system.
Another host-exercised peripheral control is the limitation on the types of commands usable within a chain of commands. For example, a well-known mode set command can include a system control bit (SC) which signifies whether or not later-occurring commands in the chain of command can be of the supervisory type, i.e. commands that result in changes of peripheral system operations such as logical partitioning of various peripheral devices, resulting in operator's control messages related to the operation of the peripheral system controls relating to multipath reconnections, purging data from buffers and the like. Such SC control lasts only for the duration of a chain of commands and for those commands occurring after receipt of a mode set command signifying the limitation. Other peripheral systems have enabled emulation of one host having a low capacity to a host having a higher capacity in the air recovery area. For example, in U.S. Pat. No. 3,721,961 a CPU type of a first class is emulated to a CPU of a second class for error recovery purposes through peripheral system action. While all of the above-described functions provide for a great diversity of data processing operations there has yet to be provided an efficient peripheral system accommodation of virtual systems having a plurality of guest operating systems of diverse types.